Processor Design Project

This is the homepage for the Processor Design Project. You can find most course information here.

This course is part of the CESE masters programme. This course is a continuation of the curriculum of Computer Arithmetic.

This course is going through some updates. For example, this website is new! If you notice any mistakes, please let us know at j.b.doenszelmann@tudelft.nl or, even better, by making an issue or pull request on https://gitlab.ewi.tudelft.nl/cese/processor-design-project/website. Especially for the Frequently asked questions, which we will keep up to date based on your questions during the labs.

Project Overview

• You do this project in groups of 3
• You can choose your own groups
• Once you have chosen a group (you can choose yourself),
  • Join a brightspace group
  • send an email to j.b.doenszelmann@tudelft.nl with three names and the email addresses linked to your dropbox account. This will give you access to a git repository and the dropbox folder in which you can upload your benchmarks

In this course, you will be tasked to improve the performance of a MIPS-based cpu in groups of 3. To evaluate your new design, you are given a set of benchmarks from the GMPbench and MiBench suites, and remote access to Zynq-7000 FPGA boards. To do so, you will receive:

1. A git repository which includes the MIPS processor VHDL code and the benchmarks, the necessary files required for simulation and FPGA implementation, as well as the MIPS cross-compiler
2. This website, detailing the project assignment and the simulation general flow and toolset.

Schedule

Getting Started

• Find a Group and let us know about it!
• Carefully read Project Workflow. It contains how information on how to do the project. It has chapters for:
  • The FPGA Board Description
  • The Vivado, the software you need to install to follow this course
  • How to test your design
• If you have questions on how to set up Vivado, or need other support, come to the weekly labs!
• In Platform description describes the MIPS processor you will be modifying in this project.
• In Frequently Asked Questions we are collecting some frequent questions. Please contribute in the labs!

Here You can find the baseline scores for all benchmarks.

Grading Procedure

The projects functionality will be verified and checked for (including between groups) plagiarism.

If the project is not functional you DO NOT pass the course. Plagiarism can also make you fail.

The final score for the project is determined based on the following criteria:

• Design Performance (DP) - The benchmark score is quite important at this point, the higher the better, but this is not the only relevant aspect. We also take into consideration the other metrics with emphasis on the compound ones which give inside on the effectiveness of your proposal, e.g., area overhead vs achieved improvement.
• Technical Merit (TM) - Aspects as innovation level and implementation quality are considered.
• Report (R) - Report organization, content, and language are important aspects at this point.
• Presentation (P) – Presentation organization, slides, and the live performance are the main metrics,

The CESE4040 final grade is computed as:

$Grade=0.35\ast DP+0.35\ast TM+0.20\ast R+0.10\ast P$